This invention relates to a novel semiconductor device structure in which the top-most layer of the device is a layer of amorphous silicon which overlies the entire semiconductor chip top structure including the bonding pads, but permits wire bonding through the amorphous silicon to underlying aluminum electrode pads.
Semiconductor devices are well known which have P-N junction patterns formed in a silicon chip, with a passivation insulation coating, for example, a deposited oxide, on the upper surface of the chip. Aluminum electrode pads are exposed through the oxide layer for connection to leads such as gate and source leads for a power MOSFET device. Such devices taking the form of an IGBT are shown, for example, in U.S. Pat. No. 5,008,725 and in copending application Ser. No. 08/041,136, filed Mar. 30, 1993, entitled POWER TRANSISTOR DEVICE HAVING ULTRA DEEP INCREASED CONCENTRATION REGION, both assigned to the assignee of the present invention.
A common problem in such devices is that moisture or humidity or other contaminants can penetrate the protective oxides, particularly at high temperatures. Thus, a conventional specification for the "HTRB" (high temperature reverse breakdown) of such devices is that their characteristics should remain stable at 85.degree. C. in a 85% humidity atmosphere. Devices which fail this test cannot be used.